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july 2010 doc id 15585 rev 4 1/40 40 viper25 off-line high voltage converters features 800 v avalanche rugged power section quasi-resonant (qr) control for valley switching operation standby power < 50 mw at 265 vac limiting current with adjustable set point adjustable and accurate overvoltage protection on-board soft-start safe auto-restart after a fault condition hysteretic thermal shutdown applications adapters for pda, camcorders, shavers, cellular phones, cordless phones, videogames auxiliary power supp ly for lcd/pdp tv, monitors, audio systems, computer, industrial systems, led driver, no el-cap led driver, utility power meter smps for set-top boxes, dvd players and recorders, white goods description the device is an off-line converter with an 800 v rugged power section, a pwm control, double levels of overcurrent protection, overvoltage and overload protections, hysteretic thermal protection, soft-start and safe auto-restart after any fault condition removal. burst mode operation and device very low consumption helps to meet the standby energy saving regulations. the quasi- resonant feature reduces emi filter cost. brown- out and brown-in function protects the switch mode power supply when the rectified input voltage level is below the normal minimum level specified for the system. the high voltage start-up circuit is embedded in the device. figure 1. typical topology so - 16 dip-7 so16 narrow %5 =&' '5$,1 *1' 9'' )% 6)0%2 '&2xwsxw9rowdjh '&,qsxw9rowdjh !-v table 1. device summary order codes package packaging VIPER25LN / viper25hn dip-7 tube viper25hd / viper25ld so16 narrow tube viper25hdtr / viper25ldtr tape and reel www.st.com
contents viper25 2/40 doc id 15585 rev 4 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 typical power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 typical electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 typical circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7 operation description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.1 power section and gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.2 high voltage startup generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.3 power-up description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.4 power-down description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.5 auto-restart description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.6 quasi-resonant operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.7 frequency foldback function and valley sk ipping mode . . . . . . . . . . . . . . 22 7.8 double blanking time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.9 starter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.10 current limit set point and feed-forward option . . . . . . . . . . . . . . . . . . . . . 24 7.11 overvoltage protection (ovp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.12 summary on zcd pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.13 feedback and overload protection (olp) . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.14 burst-mode operation at no load or very light load . . . . . . . . . . . . . . . . . . 32 7.15 brown-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.16 2nd level over current protection and hiccup mode . . . . . . . . . . . . . . . . . 34
viper25 contents doc id 15585 rev 4 3/40 8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
block diagram viper25 4/40 doc id 15585 rev 4 1 block diagram figure 2. block diagram 2 typical power 3500,9 56,/ 3500,9 4(%2-!, 3(54$/7. :#$ '.$ ,/')# ) $$ch )nternal3upplybus 2eference6oltages $2 !). /3#),,!4/2 34!24%2&2%1#,!-0 ,%" 6$$ 2 3 1 &" $%-!' ,/ ')# 3 2 1 56,/ 6in?/+ /40 /40 2 sense "2 6 "2th ) "2 hyst 6in?/+ 2 2 /#0 /60$%4%#4)/. ,/')# /60 3/&4 34!24 /60 "5234 -/$% ,/')# "5234 "5234 (6?/. (6?/. /#0 nd /#0 ?! 07- ,/')# !-v table 2. typical power part number 230 v ac 85-265 v ac adapter (1) 1. typical continuous power in non ventilated enclosed adapter measured at 50 c ambient. open frame (2) 2. maximum practical continuous power in an open fr ame design at 50 c ambient, with adequate heat sinking. adapter (1) open frame (2) viper25 18 w 20 w 10 w 12 w
viper25 pin settings doc id 15585 rev 4 5/40 3 pin settings figure 3. connection diagram (top view) note: the copper area for heat dissipation has to be designed under the drain pins. !-v table 3. pin description pin n. name function dip-7 so16 1 1...2 gnd this pin represents the device gr ound and the source of the power section. -4n.a. not available for user. it can be connected to gnd (pins 1-2) or left not connected. 25vdd supply voltage of the control section. this pin also provides the charging current of the external capacitor during power-up. 36zcd this is a multifunction pin. 1. input for the zero current detection circuit for transformer demagnetization sensing. (i.e. r lim , r ff , r ovp and d ovp , figure 32 ) 2. user defined drain current limit se t-point and voltage feed forward.the resistor, r lim , connected between zcd pin and gnd causes the current i zcd and then it limits the static maximum drain current. 3. the resistor r ff , between zcd pin and the auxiliary winding, performs the feed-forward operation and then th e drain current limitation changes according to the converter input voltage. 4. output overvoltage protection. a voltage exceeding v ovp threshold, (see table 8 on page 8 ), shuts the ic down reducing the device consumption. this function is strobed and digitally filtered for high noise immunity. 47fb control input for duty cycle control. internal current generator provides bias current for loop regulation. a voltage below the threshold v fbbm activates the burst-mode operation. a level close to the threshold v fblin means that we are approaching the cycle-by- cycle over-current set point. 58br brownout protection input with hyster esis. a voltage below the threshold v brth shuts down (not latch) the device and lowers the power consumption. device operation restarts as the voltage exceeds the threshold v brth + v brhyst . it can be connected to ground when not used. 7,8 13...16 drain high voltage drain pin. the built-in high voltage switched start-up bias current is drawn from this pin too. pins connected to the metal frame to facilitate heat dissipation.
electrical data viper25 6/40 doc id 15585 rev 4 4 electrical data 4.1 maximum ratings 4.2 thermal data table 4. absolute maximum ratings symbol pin (dip7) parameter value unit min. max. v drain 7, 8 drain-to-source (ground) voltage 800 v e av 7, 8 repetitive avalanche energy (limited by t j = 150 c) 5mj i ar 7, 8 repetitive avalanche current (limited by t j = 150 c) 1.5 a i drain 7, 8 pulse drain current (limited by t j = 150 c) 3 a v zcd 3 control input pin voltage (with i zcd = 1 ma) -0.3 self limited v v fb 4 feedback voltage -0.3 5.5 v v br 5 brown-out input pin voltage (with i br = 0.5 ma) -0.3 self limited v v dd 2 supply voltage (i dd = 25 ma) -0.3 self limited v i dd 2 input current 25 ma p tot power dissipation at t a < 40 c (dip-7) 1 w power dissipation at t a < 60 c (so16n) 1.5 w t j operating junction temperature range -40 150 c t stg storage temperature -55 150 c table 5. thermal data symbol parameter max. value so16n max. value dip7 unit r thjp thermal resistance junction pin (dissipated power = 1 w) 25 35 c/w r thja thermal resistance junction ambient (dissipated power = 1 w) 60 100 c/w r thja thermal resistance junction ambient (1) (dissipated power = 1 w) 1. when mounted on a standard si ngle side fr4 board with 100 mm 2 (0.155 sq in) of cu (35 m thick) 50 80 c/w
viper25 electrical data doc id 15585 rev 4 7/40 4.3 electrical characteristics (t j = -25 to 125 c, v dd = 14 v (a) ; unless otherwise specified) a. adjust v dd above v ddon start-up threshold before settings to 14 v. table 6. power section symbol parameter test cond ition min. typ. max. unit v bvdss break-down voltage i drain = 1 ma, v fb = gnd t j = 25 c 800 v i off off state drain current v drain = max rating, v fb = gnd 60 a r ds(on) drain-source on state resistance i drain = 0.2 a, v fb = 3 v, v br = gnd, t j = 25 c 7 i drain = 0.2 a, v fb = 3 v, v br = gnd, t j = 125 c 14 c oss effective (energy related) output capacitance v drain = 0 to 640 v 40 pf table 7. supply section symbol parameter test condition min. typ. max. unit voltag e v drain _start drain-source start voltage 60 80 100 v i ddch start-up charging current v drain = 120 v, v br = gnd, v fb = gnd, v dd = 4 v -2 -3 -4 ma v drain = 120 v, v br = gnd, v fb = gnd, v dd = 4 v after fault. -0.4 -0.6 -0.8 ma v dd operating voltage range after turn-on 8.5 23.5 v v ddclamp v dd clamp voltage i dd = 20 ma 23.5 v v ddon v dd start-up threshold v drain = 120 v, v br = gnd, v fb = gnd 13 14 15 v v ddoff v dd under voltage shutdown threshold 7.588.5v v dd(restart) v dd restart voltage threshold v drain = 120 v, v br = gnd, v fb = gnd 44.55 v current i dd0 operating supply current, not switching v fb = gnd, f sw = 0 k h z , v br = gnd, v dd = 10 v 0.9 ma i dd1 operating supply current, switching v drain = 120 v, 3.5 ma i dd_fault operating supply current, with protection tripping 400 a i dd_off operating supply current with v dd < v ddoff v dd = 7 v 270 a
electrical data viper25 8/40 doc id 15585 rev 4 table 8. controller section symbol parameter test condition min. typ. max. unit feedback pin v fbolp over load shutdown threshold 4.5 4.8 5.2 v v fblin linear dynamics upper limit 3.2 3.3 3.4 v v fbbm burst mode threshold voltage falling 0.6 v v fbbmhys burst mode hysteresis voltage rising 100 mv i fb feedback sourced current v fb = 0.3 v -150 -200 -280 ua 3.3 v < v fb < 4.8 v -3 ua r fb(dyn) dynamic resistance v fb < 3.3 v 14 19 k h fb v fb / i d 26v/a zcd pin v zcdclh upper clamp voltage i zcd = 1 ma 5 5.5 6 v v zcdath arming voltage threshold positive-going edge 0.8 v v zcdtth triggering voltage threshold negative-going edge 0.6 v i zcd internal pull-up -10 a t blank turn-on inhibit time after mosfet?s turn-off v zcd < 1 v 6.3 s v zcd >1 v 2.5 s current limitation i dlim max drain current limitation v fb = 4 v, i zcd = -10 a t j = 25 c 0.66 0.7 0.74 a t ss soft start time viper25l 3.5 ms viper25h 4.2 ms t su start up time viper25l 7.5 15 ms viper25h 9.5 18 ms t on_min minimum turn on time 220 400 480 ns td propagation delay 100 ns t leb leading edge blanking 300 ns i d_bm peak drain current during burst mode v fb = 0.6 v 160 ma overcurrent protection (2 nd ocp) i dmax second overcurrent threshold 1.2 a overvoltage protection v ovp overvoltage protection threshold 3.8 4.2 4.6 v t strobe overvoltage protection strobe time 2.2 s
viper25 electrical data doc id 15585 rev 4 9/40 oscillator section f osclim internal frequency limit viper25l 122 136 150 khz internal frequency limit viper25h 200 225 250 khz f starter starter frequency v fb =1 v, v zcd t su 1/8 f osclim khz f oscmin vfb = 1 v, v zcd > v zcda_th 1/64 f osclim khz brown-out protection v brth brown-out threshold voltage falling 0.41 0.45 0.49 v v brhyst voltage hysteresis above v brth violate rising 50 mv i brhyst current hysteresis 7 12 a v brclamp clamp voltage i br = 250 a 3 v v dis brown-out disable voltage 50 150 mv thermal shutdown t sd thermal shutdown temperature 150 160 c t hyst thermal shutdown hysteresis 30 c table 8. controller section (continued) symbol parameter test condition min. typ. max. unit
electrical data viper25 10/40 doc id 15585 rev 4 figure 4. minimum turn-on time test circuit figure 5. brown-out threshold test circuits figure 6. ovp threshold test circuits note: adjust v dd above v ddon start-up threshold before settings to 14 v 14 v 3 .5 v 50 30 v gnd zcd fb vdd drain br drain v drain i drain i dlim time time t onmin 90 % 10 % gnd zcd fb vdd drain br drain 14 v 2 v 10 k 30 v i brhyst v brth +v brhyst v brth v br i br v dis i brhyst i drain time time time gnd zcd fb vdd drain br drain v ovp v zcd v drain 14 v 2 v 10 k 30 v time time
viper25 typical electrical characteristics doc id 15585 rev 4 11/40 5 typical electrical characteristics figure 7. current limit vs t j figure 8. drain start voltage vs t j figure 9. hfb vs t j figure 10. brown-out threshold vs t j figure 11. brown-out hysteresis vs t j figure 12. brown-out hysteresis current vs t j
typical electrical characteristics viper25 12/40 doc id 15585 rev 4 figure 13. operating supply current (no switching) vs t j figure 14. operating supply current (switching) vs t j figure 15. v zcd vs i zcd figure 16. current limit vs i zcd figure 17. power mosfet on-resistance vs t j figure 18. power mosfet break down voltage vs t j 300 350 400 450 500 0.0 50.0 100.0 150.0 200.0 250.0 i zcd ( a) v zcd (mv)
viper25 typical electrical characteristics doc id 15585 rev 4 13/40 figure 19. thermal shutdown t j v dd i drain v ddon time v ddoff v dd(restart) t sd time time t sd - t hyst shut down after over temperature normal operation normal operation
typical circuits viper25 14/40 doc id 15585 rev 4 6 typical circuits figure 20. min-features qr flyback application figure 21. full-features qr flyback application ' & 9287 5 5 5 %5 & & ' & *1' 'ry s 5ry s 5 2372 %5 =&' '5 $,1 6285& ( &21752/ 9' ' )% 8 9,3(5 $&, 1 $&, 1 5 7/ ' &9'' 5/,0 & !-v !-v & 5 ' 9287 & 5 5 5 %5 & & ' & *1' '293 5293 5 2372 %5 =&' '5 $,1 6285& ( &21752/ 9' ' )% 8 9,3(5 $&, 1 $&, 1 5 7/ ' &9'' 5/,0 & 5 & 5i i 5
viper25 operation description doc id 15585 rev 4 15/40 7 operation description viper25 is a high-performance low-voltage pwm controller ic with an 800 v, avalanche rugged power section. the controller includes the current-mode pwm logic and the zcd (zero current detect) circuit for qr operation, the start-up circuitr y with soft-start feature, an oscillator for frequency foldback function, the current limit circuit with adjustable set point, the second overcurrent circuit, the burst mode manageme nt circuit, the brown-out circuit, the uvlo circuit, the auto-restart circuit and the thermal shutdown circuit. the current limit set-point is set by the zcd pin. the burst mode operation guaranties high performance in the stand-by mode and helps in the energy saving norm accomplishment all the fault protections are built in auto-restart mode with very low repetition rate to prevent ic's over heating. 7.1 power section and gate driver the power section is implemented with an avalanche ruggedness n-channel mosfet, which guarantees safe operation within the specified energy rating as well as high dv/dt capability. the power section has a bv dss of 800 v min. and a typical r ds(on) of 7 at 25 c. the integrated sensefet structure allows a virtually loss-less current sensing. the gate driver is designed to supply a controlled gate current during both turn-on and turn- off in order to minimize common mode emi. under uvlo conditions an internal pull-down circuit holds the gate low in order to ensure that the power section cannot be turned on accidentally. 7.2 high voltage startup generator the hv current generator is supplied through the drain pin and it is enabled only if the input bulk capacitor voltage is higher than v drain_start threshold, reported on table 7 on page 7 . when the hv current generator is on, the i ddch current (see table 7 on page 7 ) is delivered to the capacitor on the v dd pin. in case of auto-restart mode after a fault event, the i ddch current is reduced to 0.6 ma, in order to have a slow duty cycle during the restart phase.
operation description viper25 16/40 doc id 15585 rev 4 7.3 power-up description if the input voltage rises up till the device start level, v drain_start , the v dd voltage begins to grow due to the i ddch current (see table 7 on page 7 ) coming from the internal high voltage start-up circuit. if the v dd voltage reaches the v ddon threshold (see table 7 on page 7 ) the power mosfet starts switching and the hv current generator is turned off, see figure 23 on page 17 . the ic is powered by the energy stored in the capacitor on the vdd pin, c vdd , until when the self-supply circuit (typically an auxiliary winding of the transformer and a steering diode) develops a voltage high enough to sustain the operation. c vdd capacitor must be sized enough to avoid fast discharge and keep the needed voltage value higher than v ddoff threshold. in fact, a too low capacitance value could terminate the switching operation before th e controller receives any ener gy from the auxiliary winding. the following formula can be used for the v dd capacitor calculation: equation 1 the t ssaux is the time needed for the st eady state of the auxiliary voltage. this time is estimated by applicator according to the output stage configurations (transformer, output capacitances, etc.). during normal operation, the power mosfet is switched on immediately after transformer demagnetization, detected by the viper25, through the voltage v zcd sensed on the zcd pin. at power up the initial output voltage is zero and then the voltage v zcd is not high enough to correctly arm the internal zcd circuit. in this case, the power mosfet is turned on with a fixed frequency determined by the internal oscillator. this fixed switching frequency is f starter (see table 8 on page 8 ). as soon as the voltage on zcd pin is able to arm the zcd circuit (i.e. its positive value exceeds v zcdath ), the turn-on of the power mosfet is driven by this circuit and is no more related to the internal oscillator (except for the frequency fold-back function). the start-up phase is managed by a dedicated internal logic and is activated every time the device exits from uvlo because the v dd voltage exceeds the threshold v ddon . an internal timing (t su , see table 8 on page 8 ) defines the end of the start-up phase. during the first part of the start-up phase soft start takes place: the drain peak current is increased cycle-by-cycle from zero as far as the maximum value, i dlim , (see figure 24 or figure 25 on page 18 ). the duration of soft-start is t ss , (t ss < t su , see table 8 on page 8 ), during soft-start and until the output voltage reaches its regulated value, the feedback loop is open. to prevent an improper activation of the olp function (see the section 7.13 on page 28 ) during soft-start and until the start-up phase is over (t = t su ), the feedback voltage is clamped at v fblin. (see figure 24 on page 18 ). in this way, the feedback voltage can exceed v fblin and ramp up as far as the overload threshold, v fbolp (see figure 25 on page 18 ), which would activate the olp function , only at the end of the start-up phase (t > t su ) if the output voltage is still below the regulated value. ddoff ddon ssaux ddch vdd v v t i c ? ? =
viper25 operation description doc id 15585 rev 4 17/40 as soon as the output voltage reaches the re gulated value, the regulation loop takes over and the drain current is regulated below its limit, i dlim , by the feedback voltage, which settles at a value lower than the threshold v fblin figure 22. i dd current during start-up and burst mode figure 23. timing diagram: normal power-up and power-down sequences burst mode normal mode start- up normal mode i ddch (-3 ma) i dd1 i dd0 i dd v fbbm v fb v drain v fbbmhys v fblin v fbolp v dd v ddoff v ddon t t t t i dd v dd v drain v ddon time v in v drain_start power-on power-off normal operation regulation is lost here v in < v drain_start hv startup is no more activated v ddoff v dd(restart) i ddch (3ma) time time time
operation description viper25 18/40 doc id 15585 rev 4 figure 24. timing diagram: start-up phase and soft start (case 1) figure 25. timing diagram: start-up phase and soft start (case 2) v fb v fblin v fbolp i drain i dlim v out t t t t ss (soft start) t su (start up phase) regulated value v fb v fblin v fbolp i drain i dlim v out t t t olp-delay t t ss (soft start) t su (start up phase) regulated value
viper25 operation description doc id 15585 rev 4 19/40 7.4 power-down description at converter power-down, the system loses regula tion as soon as the input voltage is so low that the peak current limit ation is reached. the v dd voltage drops and when it falls below the v ddoff threshold the power mosfet is switched off, the energy transfers to the ic is interrupted and consequently the v dd voltages decreases, see figure 23 on page 17 . later, if the v in is lower than the threshold v drain_start , the start-up sequence is inhibited and the power-down completed. this feature is usef ul to prevent converter?s restart attempts and ensures monotonic output voltage decay during the system power-down. 7.5 auto-restart description if after a converter power-down, the v in is higher than v drain_start, the power-up sequence is not inhibited and w ill be activated only when the v dd voltage drops down the v dd(restart) threshold (reported on table 7 on page 7 ). this means that the hv start-up current generator restarts the v dd capacitor charging only when the v dd voltage drops below v dd(restart) . the scenario above described is for instance a power-down because of a fault condition. after a faul t condition, the ch arging current, i ddch , is reduced to 0.6 ma instead of 3 ma of the normal power-up conver ter phase. this feature together with the low v dd(restart) threshold (reported on table 7 on page 7 ) ensures that, after a fault, the restart attempts of the ic has a very long repe tition rate and the converter works safely with extremely low power throughput. the figure 26 shows the ic behavioral after a short circuit event. figure 26. timing diagram: behavior after short circuit i dd v dd v ds v ddon time short circuit occurs here v ddoff v dd(restart) i ddch (0.6ma) time time time v fb v fbolp v fblin t repetition 0.3 x t repetition
operation description viper25 20/40 doc id 15585 rev 4 7.6 quasi-resonant operation the control core of the viper25 is a current-mode pwm controller with a the zero current detection circuit designed for quasi-resonant (q r) operation, a techni que that provides the benefits of minimum turn-on losses, low emi emission and safe behavior in case of short circuit. at heavy load the converter operate s in quasi-resonant mode: operation lies in synchronizing mosfet's turn-on to the transformer?s demagnetization by detecting the resulting negative-going edge of the voltage across any winding of the transformer. the system works close to the boundary between discontinuous (dcm) and continuous conduction (ccm) of the transformer and the switchi ng frequency will be different for different line/load conditions. see the hyperbolic-like portion reported in figure 27 on page 21 . at medium/ light load, depending also from the co nverter input voltage, the device enters in valley-skipping mode. the internal oscillator, synchronized to mosfet?s turn-on, defines the maximum operating frequency of the converter, f osclim . the viper25 is available as type ?l? or type ?h?, depending from the value of f osclim , see table 8 on page 8 . during the normal operation the co nverter works with a frequency below f osclim , so the ?l? type is suitable for application where the prio rity is on the emi filter minimization. the ?h? type is suitable when an extended qr operation range is a plus or the priority is the transformer size reduction. as the load is reduced, and the switching frequency tends to exceeds the limit f osclim , mosfet?s turn-on will not any mo re occur on the first valley bu t on the second one, the third one and so on, see figure 29 on page 22 . in this way a ?frequency clamp? effect is achieved, piecewise linear portion in figure 27 on page 21 . when the load is extremely light or disconn ected, the converter enters in burst mode operation, see the relevant section 7.14 on page 32 . decreasing the load will then result in frequency reduction, which can go down even to few hundred hertz, thus minimizing all frequency-related losses and maki ng it easier to comply with energy saving regulations or recommendations. being the peak current low enough, no issue of audible noise. the above mentioned way of operation is based on the zcd pin. this pin is the input of the integrated zcd circuit which allows the power section turn-on at the end of the transformer demagnetization. the input signal for the zcd is obtained as a partition of the auxiliary voltage used to supply the device, see figure 28 on page 21 . when the integrated triggering circuit senses the negative going edge of the voltage v zcd , going below the threshold v zcdtth , the power mosfet is turned on with a delay that helps to achieve the minimum drain-source voltage du ring the switch on. the mentioned triggering circuit has to be previously armed by a positive going edge of the voltage v zcd , exceeding the threshold v zcdath . see the table 8 on page 8 . after the mosfet turn-off there is a typical noise generated by the transformer's leakage inductance resonance ringing and coupled wi th the zcd pin. the blanking time, t blank , helps to filter this noise avoiding false triggers of the zcd circuit.
viper25 operation description doc id 15585 rev 4 21/40 figure 27. switching frequency vs output load figure 28. zero current detection circuit and oscillator circuit f 37 0out f /3#lim )n p ut6olta g e 1uasi 2esonant-ode 6alle y 3ki pp in g -ode "urst-ode 1uasi 2esonant-odewithout frequency&old back&eature !-v :#$ 6$$ 6 6 4",!.+ $%,!9 -onostable 3% 2% 1 1 'ate $river &rom07-#omparator /3#),,!4/2 ?& /3# 3tarter3ignal & /3# &req&old"ack 2eset/scillator 3tart4",!.+at-/3&%44urnoff '.$ $2!). !uxiliary 7inding ! " # $ % & !-v
operation description viper25 22/40 doc id 15585 rev 4 7.7 frequency foldback function and valley skipping mode the switching frequency, in quasi resonant mo de, is not fixed and it depends on both the load and the converter?s input voltage. the sw itching frequency incr eases when the load decreases, or when the input voltage mains increases, and vice versa. in principle it could reach an infinite value. to avoid that, the viper25 taps the maximum switching frequency of the application by its control logic. the frequency limit is realized with an internal oscillator sw itching at 136 khz for viper25l or at 225 khz for the viper25h, sees the parameter f osclim on table 8 on page 8 . this oscillator is synchronized with power mosfet turn-on. when the power mo sfet is off, if the first negative-going edge voltage of the zcd pin, resulting from transformer?s demagnetization, appears afte r at least one oscillator c ycle has been completed, the mosfet is turned on and th e oscillator re-synchronized. otherwise, if the first negativ e-going edge voltage appears before comp leting one oscillator cycle, the signal is ignored. due to the ringing of the drain voltage, the zcd pin will experience another positive-going edge volt age that arms the circuit and a subsequent negative-going edge voltage. agai n, if this appears before the oscillator cycle is complete, it is ignored, otherwise the mosfet is turned on and the oscilla tor re-synchronized. in this way, one or more drain ring ing cycles will be skipped ( figure 29 on page 22 shows the so called ?valley-skipping mode?) an d the switching frequency will be prevented from exceeding the limit f osclim . figure 29. drain ringing cycle skipping as the load is progressively reduced when the system operates in valley skipping-mode, uneven switching cycles may be observed under some line/load conditions, due to the fact that the off-time of the power mosfet is allowed to change with discrete steps of one ringi ng cycle, while the off-time needed for cycle-by-cycle energy balance could fall in between. thus one or more longer switching cycles will be compen sated by one or more shorter cycles and vice versa. this mechanism is natural and there is no appreci able effect on the converter?s performances and on its output voltage. the operation described so far does not consider the blanking time t blank after power mosfet's turn off. actually t blank does not come into play as long as the following condition is met: equation 2 where d is the mosfet duty c ycle. if this condition is no t met, the time during which mosfet's turn-on is inhibited is extended beyond t osclim by a fraction of t blank . as a consequence, the maximum switch ing frequency will be a little lo wer than the internal limit set by the oscillator and valley-skipping mode will take place slightly earlier than expected. ? p in = p in' (limit condit ion) p in = p in'' < p in' p in = p in''' < p in'' t v ds t fw t os c t v t on t v ds t osc t v ds t os c lim osc blank lim osc blank f t 1 t t 1 d ? ? = ?
viper25 operation description doc id 15585 rev 4 23/40 7.8 double blanking time the blanking time, t blank , can have two different values: the lower one is 2,5 s (typical value) and the higher one is 6,3 s (typical value). the value is linked to the voltage v zcd , sampled during the time t strobe defined as for the over voltage protection (see the relevant section 7.11 on page 26 ). the time t blank has the lower value if is detected v zcd < 1v or it has the higher value if is detected v zcd > 1v, refer to table 8 on page 8 and figure 30 on page 23 . the higher value of the blanking time is normally activated during the start-up phase or in case of output short circuit; when the output voltage of the converter is quite lower than the regulated value. in this condition can happe ns that during the demagnetization of the transformer, the v zcd is very close to the arming and triggering thresholds (v zcdath and v zcdtth ) and the zcd circuit can be erroneously trigged, leading the system to work at higher frequency and in continuous mode. this false trigger is inhibited by the selection of the higher value of t blank when v zcd is lower than 1 v. during the normal operation, in steady state condition, the voltage v zcd during the demagnetization is higher than 1v and the selected t blank value is the lower one. the figure 30 shows the typical waveforms during the power up and the linked t blank selection. figure 30. double t blank timing diagram vaux 1 v t 0 zc d (pin 3) 1.5 0.5 t blank c t t t t t t d a t st r o b e 6.3 s 2. 5 s f dela y mosfet swit ched on by the starte r quasi resonant operation lim os c f 4 t 0.8 v 0. 6 v
operation description viper25 24/40 doc id 15585 rev 4 7.9 starter if the amplitude of the voltage on zcd pin at th e end of one oscillator cycle is smaller than the v zcdath arming threshold, in which case mosfet's turn-on could not be triggered, the system would stop. this is what normally happens during converte r?s power-up or under overload/short circuit conditions. during the converter?s startup phase, the voltage on zcd pin is not high enough to arm the triggering circuit. thus, the converter operates at a fixed frequency, f starter (see ta b l e 8 on page 8 ). as the voltage develope d across the auxiliary wind ing becomes hi gh enough to arm the zcd circuit, mosfet's turn-on is locked to transformer demagnetization, hence setting up quasi-resonant operation. as protection, in case the zcd voltage is permanently above the threshold v zcdath , the switching frequency is reduce d to the minimum value, f oscmin , reported on ta b l e 8 o n page 8 . 7.10 current limit set point and feed-forward option the viper25 is a current mode converter and the drain current is limited cycle by cycle according to the fb pin voltage value that is related with the feedback loop response and the load. when the drain current, sensed by the integrated sense-fe t, reaches the current limitation, after the internal propagation dela y, the mosfet is switched off. the current limitation cannot exceed a certain value, i dlim , that can be adjusted acting on the current sunk from the zcd pin during mosfet?s on-time. usually a resistor, r lim , connected from zcd pin to ground is used to fix this sunk current and then the peak drain current set-point: the lower the resistor is, the lower i dlim will be. for a qr fly-back converter the power capabilit y strongly depends on th e input voltage. in wide-range applications at maximum line the power capability can be more than twice the value at minimum line, as shown by the upper curve in the diagram of figure 31 on page 25 . to reduce this dependence, the current limit i dlim has to be reduced according to the increment of the input voltage, implementing the so called line feed-forward. it?s realized with a resistor, r ff , connected between th e zcd pin and the auxilia ry winding, see the figure 32 on page 26 . since the voltage across the auxiliary winding during mosfet?s on-time is proportional to the input voltage throug h the auxiliary-to-primary turns ratio n aux /n p , a current proportional to the input voltage is su nk from the zcd pin, thus lowering the over current set point.
viper25 operation description doc id 15585 rev 4 25/40 figure 31. typical power capability vs input voltage in quasi-resonant converter?s in order to proper select the value of the resistance r ff (see figure 32 on page 26 ), once are known the proper i dlim set points at minimum and at the maximum converter input voltage. the following approximated formula calculates the value of the resistor r ff equation 3 where: v in_max and v in_min are the maximum and minimum converter rectified input voltage n aux is the primary to auxiliary winding turn ratio i zcd1 , and i zcd2 are the currents needed to sink from the zcd pin, in order to obtain the selected i dlim set points, respectively at v in_max and v in_min , the graph i dlim vs i zcd current is reported on figure 16 on page 12 ). the r lim value can be calculated from the following formula knowing the r ff value: equation 4 where: v zcd1 and v zcd2 are the zcd pin voltages w hen the sunk current is i zcd1 and i zcd2 respectively (see figure 15 on page 12 ). ? v in v inmi n p inli m @ v inmi n 11.522.53 3.54 0.5 1 1.5 2 2.5 system optimally compensated sy s tem not compensated ) i i ( n v v r 2 zcd 1 zcd aux min _ in max _ in ff ? ? ? = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? + ? = ff 2 zcd aux max _ in 2 zcd 2 zcd ff 1 zcd aux min _ in 1 zcd 1 zcd lim r v n v i v , r v n v i v max r
operation description viper25 26/40 doc id 15585 rev 4 figure 32. zcd pin typical external configuration 7.11 overvoltage protection (ovp) the viper25 has integrated the logic for the monitor of the output voltage using as input signal the voltage v zcd during the off time of the power mosfet. this is the time when the voltage from the auxiliary winding tracks the output voltage, through the turn ratio n aux / n sec . the zcd pin has to be connected to the auxiliary winding th rough the diode d ovp and the resistors r ovp and r lim as shows the figure 32 on page 26 . when, during the off time, the voltage v zcd exceeds, four consecutive times, the reference voltage v ovp (reported on table 8 on page 8 ) the over voltage protection w ill stop the power mosfet and the converter enters the auto-restart mode. in order to bypass the noise after the tu rn off of the power mosfet, the voltage v zcd is sampled inside a short window after the time t strobe , see the table 8 on page 8 and figure 33 on page 27 . the sampled signal, if higher than v ovp , trigger the internal ovp digital signal and increments the internal counte r. the same counter is reset every time the signal ovp is not triggered in one oscillator cycle. referring to the figure 32 , the resistors divider ratio k ovp will be given by: equation 5 =&' &rom3ense&%4 $ /60 4o/600rotection 2 && !uxiliary 7inding 2 ,)- 4o07-,ogic 4ransformer demagnetization sensin g /60 3ensing #urrentlimit setpoint 3oftstart 2 /60 $ !58 9'' !-v k ovp v ovp n aux n sec -------------- v outovp v dsec + () v daux ? ? -------------------------------------------------------------------------------------------------- - =
viper25 operation description doc id 15585 rev 4 27/40 equation 6 where: v ovp is the ovp threshold (see table 8 on page 8 ) v out ovp is the converter output voltage value to activate the ovp (set by designer) designer n aux is the auxiliary winding turns n sec is the secondary winding turns v dsec is the secondary diode forward voltage v daux is the auxiliary diode forward voltage r ovp together r lim make the output voltage divider than, fixed r lim, according to the desired i dlim , the r ovp can be calculating by: equation 7 the resistor values will be such that the current sourced and sunk by the zcd pin be within the rated capability of the internal clamp. figure 33. ovp timing diagram k ovp r lim r lim r ovp + ---------------------------------- = r ovp r lim 1k ovp ? k ovp ---------------------- - = t va u x v ovp t t t s trobe t counter re s et t counter s tatu s t 0 zcd 2 s 0.5 s ovp fault 0 0 0 0 1 1 2 2 0 0 1 1 2 2 3 3 4 0 e r u l i a f p o o l k c a b d e e f e c n a b r u t s i d y r a r o p m e t n o i t a r e p o l a m r o n t t t t s trobe t counter re s et t counter s tatu s t 0 2 s 0.5 s ovp fault 0 0 0 0 1 1 2 2 0 0 1 1 2 2 3 3 4 0 e r u l i a f p o o l k c a b d e e f e c n a b r u t s i d y r a r o p m e t n o i t a r e p o l a m r o n t
operation description viper25 28/40 doc id 15585 rev 4 7.12 summary on zcd pin referring to the figure 32 on page 26 , the circuitry connected to the zcd pin enables to implement the following functions: 1. current limit, i dlim , set point 2. line feed-forward compensation 3. output overvoltage protection (ovp) 4. zero current dete ction for qr operation chosen r lim , r ff and r ovp as described in previous paragraphs this function are automatically defined. ta bl e 9 refers to the figure 32 and list the external resistance combinations needed to activate one or more functions associated to the zcd pin. 7.13 feedback and overload protection (olp) the feedback pin (fb) controls the pwm operat ion, enters the burst mode and manages the delayed overload protection. the thresholds v fbbm and v fblin (reported on table 8 on page 8 ) are respectively the low and the high limit of the pwm operations, w here the drain current is sensed trough the integrated resistor r sense and applied to the comparator pwm. the pwm logic turns off the power mosfet as soon as the sensed voltage is equal to the voltage applied to the fb pin and trough the integrated resistors network, see the figure 2 on page 4 and figure 20 on page 14 . as shows the ic block diagram reported in figure 2 on page 4 , in parallel with the pwm comparator there is the ocp comparator that limits the drain current as maximum to the value i dlim , reported on table8 on page8 . in case of higher load the voltage v fb increases, when it reaches the threshold v fblin the drain current is limited to i dlim and the internal current starts the charge of the capacitor c fb . as soon as the voltage v fb reaches the threshold v fbolp , see figure 36 on page 31 , the protection turns off the ic. after, the auto-restart mode is activated using the low value of the current i ddch , see table 7 on page 7 . table 9. zcd pin configurations function / component r lim r ovp r ff d ovp i dlim set point see equation 4 required for zcd not required yes ovp 22 k see equation 7 not required yes line feed-forward 22 k required for zcd see equation 3 ye s i dlim set point and ovp see equation 4 with r ff = see equation 7 not required yes ovp and line feed-forward 22 k see equation 7 see equation 3 ye s i dlim set point and line feed-forward see equation 4 required for zcd see equation 3 ye s i dlim reduction+ ovp + line feed-forward see equation 4 see equation 7 see equation 3 ye s
viper25 operation description doc id 15585 rev 4 29/40 the time, from the high load detection, v fb = v fblin , to the over load turn-off, v fb = v fbolp , depends from the value of the capacitor c fb and from the internal charge current, i fb . the olp delay time can be calculating by the formula: equation 8 the current, i fb , is 3 a as minimum value. the componen ts connected to the fb pin are also a part of the compensation loop , so they have to be sele cted taking into account the proper delay and loop stability consideration. the figure 34 on page 30 and figure 35 on page 30 show two different feedback networks. in the figure 33 on page 27 , the capacitor, c fb , connected to fb pin is used as part of the circuit to compensate the feedback loop but al so as element to delay the olp shut down owing to the time needed to charge the capacitor (see the equation 8 ). after the start-up time, t su , during which the feedback voltage is fixed at v fblin , the output capacitor could not be at its nominal value and the controller interpreter this situation as an over load condition. in this case, the olp delay helps to avoi d an incorrect device shut down during the start-up. see the relevant section 7.3 on page 16 . owing to the above considerations, the olp delay time must be long enough to by-pass the initial output voltage transient and check the over load condition only when the output voltage is in steady state. the output transien t time depends from the value of the output capacitor and from the load. when the value of the c fb capacitor calculated fo r the loop stability is too low and cannot ensure enough olp delay, an alternative compensation network can be used and it is showed in figure 35 on page 30 . using this alternative compensation network, two poles (f pfb , f pfb1 ) and one zero (f zfb ) are introduced by the capacitors c fb and c fb1 and the resistor r fb1 . the capacitor c fb introduces a pole (f pfb ) at higher frequency than f zb and f pfb1 . this pole is usually used to compensate the high freq uency zero due to the esr (equivalent series resistor) of the output capacitance of the fly-back converter. the mathematical expressions of these poles and zero frequency, considering the scheme in figure 35 on page 30 are reported by the equations below: equation 9 equation 10 t olp delay ? c fb v fbolp v fblin ? 3 a --------------------------------------- - = 1 fb 1 fb zfb r c 2 1 f ? ? ? = () 1 fb ) dyn ( fb fb 1 fb ) dyn ( fb pfb r r c 2 r r f ? ? ? ? + =
operation description viper25 30/40 doc id 15585 rev 4 equation 11 the r fb(dyn) is the dynamic resistance seen by the fb pin and reported on ta bl e 8 o n page 8 . the c fb1 capacitor fixes the olp delay and usually c fb1 results much higher than c fb . the equation 8 on page 29 can be still used to calculat e the olp delay time but c fb1 has to be considered instead of c fb . using the alternative compensation network, the designer can satisfy, in all case, the loop stabilit y and the enough olp delay time alike. figure 34. fb pin configuration figure 35. fb pin configuration () ) dyn ( fb 1 fb 1 fb 1 pfb r r c 2 1 f + ? ? ? = from sense fet 4.8v burst pwm control cfb to pwm logic burst-mode references burst-mode logic + - pwm + - olp comparator to disable logic 4.8v from sense fet pwm control + - pwm burst to disable logic + - olp comparator to pwm logic burst-mode logic cfb1 rfb1 cfb burst-mode references
viper25 operation description doc id 15585 rev 4 31/40 figure 36. timing diagram: overload protection t t t t soft start start up over load warning over load warning i out v out i drain v fb stop operation i dlim v fblin v fbolp
operation description viper25 32/40 doc id 15585 rev 4 7.14 burst-mode operation at no load or very light load when the load decrease the feedback loop reacts lowering the feedback pin voltage. if it falls down the burst mode threshold, v fbbm , the power mosfet is not more allowed to be switched on. after the mosfet stops, as a result of the feedback reaction to the energy delivery stop, the feedback pin voltage increases and exceeding the level, v fbbm + v fbbmhys , the power mosfet starts switching again. the burst mode thresholds are reported on ta b l e 8 and figure 37 shows this behavior. systems alternates period of time where power mosfet is switching to period of time where power mosfet is not switching; this device working mode is the burst mode. the power delivered to output during switching periods exceeds the load power demands; the excess of power is balanced from not switching period where no power is processed. the advantage of burst mode operation is an average switching frequency much lower then the normal operation working frequency, up to some hundred of hertz, minimizing all frequency related losses. during the burst-mode the drain current peak is clamped to the level, i d_bm , reported on ta bl e 8 . figure 37. burst mode timing diagram, light load management 7.15 brown-out protection brown-out protection is a not-latched shutdown function activated when a condition of mains under voltage is detected. the brown-out comparator is internally referenced to v brth threshold, see table 8 on page 8 , and disables the pwm if the voltage applied at the br pin is below this internal referenc e. under this condition the powe r mosfet is turned off. until the brown out condition is present, the v dd voltage continuously oscillates between the v ddon and the uvlo thresholds, as shown in the timing diagram of figure 38 on page 33 . a voltage hysteresis is present to improve the noise immunity. the switching operation is restarted as the volt age on the pin is above the reference plus the before said voltage hysteresis. see figure 5 on page 10 . the brown-out comparator is provided also with a current hysteresis, i brhyst . the designer has to set the rectified input voltage above which the power mosfet starts switching after brown out event, v inon , and the rectified input voltage below which the power mosfet is switched off, v inoff . thanks to the i brhyst , see table 8 on page 8 , these two thresholds can be set separately. time time time v comp v fbbm +v fbbmhys v fbbm i dd1 i dd0 i dd i drain i d_bm burst mode
viper25 operation description doc id 15585 rev 4 33/40 fixed the v inon and the v inoff levels, with reference to figure 38 , the following relationships can be established for the calculation of the resistors r h and r l : equation 12 equation 13 for a proper operation of this function, v in on must be less than the peak voltage at minimum mains and v in off less than the minimum voltage on the input bulk capacitor at minimum mains and maximum load. the br pin is a high impedance input connected to high value resistors, thus it is prone to pick up noise, which might alter the off threshold when the converter operates or gives origin to undesired switch-off of the device during esd tests. it is possible to bypass the pin to ground with a small film capacitor (e.g. 1-10 nf) to prevent any malfunctioning of this kind. if the brown-out function is not used the br pi n has to be connected to gnd, ensuring that the voltage is lower than the minimum of v dis threshold (50 mv, see ta bl e 8 ). in order to figure 38. brown-out protection: br external setting and timing diagram - + disable c br v dis - + v in_ok v brth r h i brhyst r l v in_dc vdd + v out v in v inon v inoff v drain_start v br v in_ok i br v brth i brhyst v dd v ddon v ddoff v ds v dd(restart) brhyst brth brth inoff brhyst inoff inon brhyst brhyst l i v v v v v v i v r ? ? ? + ? = brhyst brhyst l l brhyst brhyst inoff inon h i v r r i v v v r + ? ? =
operation description viper25 34/40 doc id 15585 rev 4 enable the brown-out function the br pin voltage has to be higher than the maximum of v dis threshold (150 mv, see ta b l e 8 ). 7.16 2 nd level over current protection and hiccup mode the viper25 is protected against short circuit of the secondary rectifier, short circuit on the secondary winding or a hard-saturation of fly-back transformer. such as anomalous condition is invoked when the drain current exceed the threshold i dmax , see ta bl e 8 o n page 8 . to distinguish a real malfunction from a disturbance (e.g. induced during esd tests) a ?warning state? is entered after the first signal trip. if in the subsequent switching cycle the signal is not tripped, a temp orary disturbance is assumed and the protection logic will be reset in its idle state; otherwise if the i dmax threshold is exceeded for two consecutive switching cycles a real malfunction is assumed and the power mosfet is turned off. the shutdown condition is latched as long as the device is supplied. while it is disabled, no energy is transferred from the auxiliary winding; h ence the voltage on the v dd capacitor decays till the v dd under voltage threshold (v ddoff ), which clears the latch. the start up hv current generator is still off, until v dd voltage goes below its restart voltage, v dd(restart) . after this condition the v dd capacitor is charged again by 600 a current, and the converter switching restarts if the v ddon occurs. if the fault condition is not removed the device enters in auto-restart mode. this behavioral results in a low-frequency intermittent operation (hiccup-mode operation) , with very low stress on the power circuit. see the timing diagram of figure 39 . figure 39. hiccup-mode ocp: timing diagram vcc v drain i drain s econd a ry diode i s s horted here t t t dmax on off (re s tart) s econd a ry diode i s s horted here t t t i v dd v dd v dd v dd
viper25 package mechanical data doc id 15585 rev 4 35/40 8 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. note: 1 the leads size is comprehensive of the thickness of the leads finishing material. 2 dimensions do not include mold protrusion, not to exceed 0,25 mm in total (both side). 3 package outline exclusive of metal burrs dimensions. 4 datum plane ?h? coincident with the bottom of lead, where lead exits body. 5 ref. poa mother doc. 0037880 table 10. dip-7 mechanical data dim. mm typ. min. max. a 5.33 a1 0.38 a2 3.30 2.92 4.95 b 0.46 0.36 0.56 b2 1.52 1.14 1.78 c 0.25 0.20 0.36 d 9.27 9.02 10.16 e 7.87 7.62 8.26 e1 6.35 6.10 7.11 e 2.54 ea 7.62 eb 10.92 l 3.30 2.92 3.81 m (1)(2) 1. creepage distance > 800 v 2. creepage distance as shown in the 664-1 cei / iec standard 2.508 n 0.50 0.40 0.60 n1 0.60 o (2)(3) 3. creepage distance 250 v 0.548
package mechanical data viper25 36/40 doc id 15585 rev 4 figure 40. dip-7 package dimensions
viper25 package mechanical data doc id 15585 rev 4 37/40 table 11. so16 narrow mechanical data dim. databook (mm.) min. typ. max. a 1.75 a1 0.1 0.25 a2 1.25 b 0.31 0.51 c 0.17 0.25 d 9.8 9.9 10 e 5.8 6 6.2 e1 3.8 3.9 4 e 1.27 h 0.25 0.5 l 0.4 1.27 k 0 8 ccc 0.1
package mechanical data viper25 38/40 doc id 15585 rev 4 figure 41. so16 package dimensions
viper25 revision history doc id 15585 rev 4 39/40 9 revision history table 12. document revision history date revision changes 17-apr-2009 1 initial release 09-jun-2009 2 updated application paragraph in coverpage and table 8 on page 8 26-aug-2009 3 content reworked to improve readability, no technical changes 21-jul-2010 4 updated table 8 on page 8 and figure 38 on page 33
viper25 40/40 doc id 15585 rev 4 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2010 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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